Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study
- DOI
- 10.1109/norcas64408.2024.10752460
- Published
- 2024-10-29
- Container
- 2024 IEEE Nordic Circuits and Systems Conference (NorCAS)
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/norcas64408.2024.10752460,
title = {Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study},
author = {Mohammad Reza Heidari Iman and Sallar Ahmadi-Pour and Rolf Drechsler and Tara Ghasempouri},
year = {2024},
journal = {2024 IEEE Nordic Circuits and Systems Conference (NorCAS)},
doi = {10.1109/norcas64408.2024.10752460},
url = {https://doi.org/10.1109/norcas64408.2024.10752460}
}RIS
TY - JOUR TI - Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study AU - Mohammad Reza Heidari Iman AU - Sallar Ahmadi-Pour AU - Rolf Drechsler AU - Tara Ghasempouri PY - 2024 JO - 2024 IEEE Nordic Circuits and Systems Conference (NorCAS) DO - 10.1109/norcas64408.2024.10752460 UR - https://doi.org/10.1109/norcas64408.2024.10752460 ER -
APA
Iman, M. R. H., Ahmadi-Pour, S., Drechsler, R., & Ghasempouri, T. (2024). Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study. 2024 IEEE Nordic Circuits and Systems Conference (NorCAS). https://doi.org/10.1109/norcas64408.2024.10752460
Source records
- crossref · retrieved 2026-11-10T15:12:44.344Z