FVM: A Formal Verification Methodology for VHDL Designs

Hipólito Guzmán-Miranda, Marcos López García, Alberto Urbón Aguado

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DOI: 10.1109/ojcs.2025.3625468
Published: 2025
Container: IEEE Open Journal of the Computer Society
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1109/ojcs.2025.3625468,
  title = {FVM: A Formal Verification Methodology for VHDL Designs},
  author = {Hipólito Guzmán-Miranda and Marcos López García and Alberto Urbón Aguado},
  year = {2025},
  journal = {IEEE Open Journal of the Computer Society},
  doi = {10.1109/ojcs.2025.3625468},
  url = {https://doi.org/10.1109/ojcs.2025.3625468}
}

RIS

TY  - JOUR
TI  - FVM: A Formal Verification Methodology for VHDL Designs
AU  - Hipólito Guzmán-Miranda
AU  - Marcos López García
AU  - Alberto Urbón Aguado
PY  - 2025
JO  - IEEE Open Journal of the Computer Society
DO  - 10.1109/ojcs.2025.3625468
UR  - https://doi.org/10.1109/ojcs.2025.3625468
ER  -

APA

Guzmán-Miranda, H., García, M. L., & Aguado, A. U. (2025). FVM: A Formal Verification Methodology for VHDL Designs. IEEE Open Journal of the Computer Society. https://doi.org/10.1109/ojcs.2025.3625468

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crossref · retrieved 2026-11-10T10:32:41.641Z