Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits
- DOI
- 10.1109/sbcci66862.2025.11218679
- Published
- 2025-08-25
- Container
- 2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/sbcci66862.2025.11218679,
title = {Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits},
author = {Jéssica Gonsalves Santos and Ismael de Almeida Junior and Sylvain Engels and Robin Wilson and Laurent Fesquet},
year = {2025},
journal = {2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)},
doi = {10.1109/sbcci66862.2025.11218679},
url = {https://doi.org/10.1109/sbcci66862.2025.11218679}
}RIS
TY - JOUR TI - Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits AU - Jéssica Gonsalves Santos AU - Ismael de Almeida Junior AU - Sylvain Engels AU - Robin Wilson AU - Laurent Fesquet PY - 2025 JO - 2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI) DO - 10.1109/sbcci66862.2025.11218679 UR - https://doi.org/10.1109/sbcci66862.2025.11218679 ER -
APA
Santos, J. G., Junior, I. D. A., Engels, S., Wilson, R., & Fesquet, L. (2025). Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits. 2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI). https://doi.org/10.1109/sbcci66862.2025.11218679
Source records
- crossref · retrieved 2026-09-26T22:42:58.770Z