Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications
- DOI
- 10.1109/tbcas.2018.2871184
- Published
- 2018-12
- Container
- IEEE Transactions on Biomedical Circuits and Systems
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/tbcas.2018.2871184,
title = {Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications},
author = {Jui-Hung Hsieh and Meng-Ju Shih and Xin-Hao Huang},
year = {2018},
journal = {IEEE Transactions on Biomedical Circuits and Systems},
doi = {10.1109/tbcas.2018.2871184},
url = {https://doi.org/10.1109/tbcas.2018.2871184}
}RIS
TY - JOUR TI - Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications AU - Jui-Hung Hsieh AU - Meng-Ju Shih AU - Xin-Hao Huang PY - 2018 JO - IEEE Transactions on Biomedical Circuits and Systems DO - 10.1109/tbcas.2018.2871184 UR - https://doi.org/10.1109/tbcas.2018.2871184 ER -
APA
Hsieh, J., Shih, M., & Huang, X. (2018). Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications. IEEE Transactions on Biomedical Circuits and Systems. https://doi.org/10.1109/tbcas.2018.2871184
Source records
- crossref · retrieved 2026-09-26T12:26:31.067Z