Lightweight Hardware Architectures for the Present Cipher in FPGA
- DOI
- 10.1109/tcsi.2017.2686783
- Published
- 2017-09
- Container
- IEEE Transactions on Circuits and Systems I: Regular Papers
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/tcsi.2017.2686783,
title = {Lightweight Hardware Architectures for the Present Cipher in FPGA},
author = {Carlos Andres Lara-Nino and Arturo Diaz-Perez and Miguel Morales-Sandoval},
year = {2017},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
doi = {10.1109/tcsi.2017.2686783},
url = {https://doi.org/10.1109/tcsi.2017.2686783}
}RIS
TY - JOUR TI - Lightweight Hardware Architectures for the Present Cipher in FPGA AU - Carlos Andres Lara-Nino AU - Arturo Diaz-Perez AU - Miguel Morales-Sandoval PY - 2017 JO - IEEE Transactions on Circuits and Systems I: Regular Papers DO - 10.1109/tcsi.2017.2686783 UR - https://doi.org/10.1109/tcsi.2017.2686783 ER -
APA
Lara-Nino, C. A., Diaz-Perez, A., & Morales-Sandoval, M. (2017). Lightweight Hardware Architectures for the Present Cipher in FPGA. IEEE Transactions on Circuits and Systems I: Regular Papers. https://doi.org/10.1109/tcsi.2017.2686783
Source records
- crossref · retrieved 2026-11-10T01:24:55.670Z