High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines
- DOI
- 10.1109/tnn.2010.2073481
- Published
- 2010-11
- Container
- IEEE Transactions on Neural Networks
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/tnn.2010.2073481,
title = {High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines},
author = {Daniel Le Ly and Paul Chow},
year = {2010},
journal = {IEEE Transactions on Neural Networks},
doi = {10.1109/tnn.2010.2073481},
url = {https://doi.org/10.1109/tnn.2010.2073481}
}RIS
TY - JOUR TI - High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines AU - Daniel Le Ly AU - Paul Chow PY - 2010 JO - IEEE Transactions on Neural Networks DO - 10.1109/tnn.2010.2073481 UR - https://doi.org/10.1109/tnn.2010.2073481 ER -
APA
Ly, D. L., & Chow, P. (2010). High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. IEEE Transactions on Neural Networks. https://doi.org/10.1109/tnn.2010.2073481
Source records
- crossref · retrieved 2026-09-26T14:26:49.532Z