Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
- DOI
- 10.1109/tqe.2024.3512367
- Published
- 2025
- Container
- IEEE Transactions on Quantum Engineering
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/tqe.2024.3512367,
title = {Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures},
author = {Shivendra Singh Parihar and Girish Pahwa and Baker Mohammad and Yogesh Singh Chauhan and Hussam Amrouch},
year = {2025},
journal = {IEEE Transactions on Quantum Engineering},
doi = {10.1109/tqe.2024.3512367},
url = {https://doi.org/10.1109/tqe.2024.3512367}
}RIS
TY - JOUR TI - Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures AU - Shivendra Singh Parihar AU - Girish Pahwa AU - Baker Mohammad AU - Yogesh Singh Chauhan AU - Hussam Amrouch PY - 2025 JO - IEEE Transactions on Quantum Engineering DO - 10.1109/tqe.2024.3512367 UR - https://doi.org/10.1109/tqe.2024.3512367 ER -
APA
Parihar, S. S., Pahwa, G., Mohammad, B., Chauhan, Y. S., & Amrouch, H. (2025). Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures. IEEE Transactions on Quantum Engineering. https://doi.org/10.1109/tqe.2024.3512367
Source records
- crossref · retrieved 2026-11-10T11:08:23.523Z