Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers.
- DOI
- 10.1109/tvlsi.2018.2883642
- Published
- 2019 Apr
- Container
- IEEE transactions on very large scale integration (VLSI) systems
- Publisher
- Not recorded
- Open access
- yes
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Cite this work
BibTeX
@article{allodium:10.1109/tvlsi.2018.2883642,
title = {Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers.},
author = {Mostafa S and John EB and Panday MM},
year = {2019},
journal = {IEEE transactions on very large scale integration (VLSI) systems},
doi = {10.1109/tvlsi.2018.2883642},
url = {https://doi.org/10.1109/tvlsi.2018.2883642}
}RIS
TY - JOUR TI - Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers. AU - Mostafa S AU - John EB AU - Panday MM PY - 2019 JO - IEEE transactions on very large scale integration (VLSI) systems DO - 10.1109/tvlsi.2018.2883642 UR - https://doi.org/10.1109/tvlsi.2018.2883642 ER -
APA
S, M., EB, J., & MM, P. (2019). Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers.. IEEE transactions on very large scale integration (VLSI) systems. https://doi.org/10.1109/tvlsi.2018.2883642
Source records
- pubmed · retrieved 2026-09-25T16:23:34.147Z
- europe-pmc · retrieved 2026-09-25T16:23:34.165Z