Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers
- DOI
- 10.1109/tvlsi.2018.2883642
- Published
- 2019-04
- Container
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/tvlsi.2018.2883642,
title = {Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers},
author = {Safwat Mostafa Noor and Eugene John and Manoj Panday},
year = {2019},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
doi = {10.1109/tvlsi.2018.2883642},
url = {https://doi.org/10.1109/tvlsi.2018.2883642}
}RIS
TY - JOUR TI - Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers AU - Safwat Mostafa Noor AU - Eugene John AU - Manoj Panday PY - 2019 JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems DO - 10.1109/tvlsi.2018.2883642 UR - https://doi.org/10.1109/tvlsi.2018.2883642 ER -
APA
Noor, S. M., John, E., & Panday, M. (2019). Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/tvlsi.2018.2883642
Source records
- crossref · retrieved 2026-11-10T15:05:21.292Z