Analysis of on-chip communication properties in accelerator architectures for deep neural networks

Hana Krichene, Jean-Marc Philippe

Open source

DOI
10.1145/3479876.3481588
Published
2021-10-08
Container
Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip
Publisher
ACM
Open access
unknown

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BibTeX

@article{allodium:10.1145/3479876.3481588,
  title = {Analysis of on-chip communication properties in accelerator architectures for deep neural networks},
  author = {Hana Krichene and Jean-Marc Philippe},
  year = {2021},
  journal = {Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip},
  doi = {10.1145/3479876.3481588},
  url = {https://doi.org/10.1145/3479876.3481588}
}

RIS

TY  - JOUR
TI  - Analysis of on-chip communication properties in accelerator architectures for deep neural networks
AU  - Hana Krichene
AU  - Jean-Marc Philippe
PY  - 2021
JO  - Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip
DO  - 10.1145/3479876.3481588
UR  - https://doi.org/10.1145/3479876.3481588
ER  - 

APA

Krichene, H., & Philippe, J. (2021). Analysis of on-chip communication properties in accelerator architectures for deep neural networks. Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip. https://doi.org/10.1145/3479876.3481588

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