Performance analysis of CMOS based analog circuit design with PVR variation
- DOI
- 10.11591/eei.v12i1.4357
- Published
- 2023-02-01
- Container
- Bulletin of Electrical Engineering and Informatics
- Publisher
- Institute of Advanced Engineering and Science
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.11591/eei.v12i1.4357,
title = {Performance analysis of CMOS based analog circuit design with PVR variation},
author = {Pankaj P. Prajapati and Anilkumar J. Kshatriya and Sureshbhai L. Bharvad and Abhay B. Upadhyay},
year = {2023},
journal = {Bulletin of Electrical Engineering and Informatics},
doi = {10.11591/eei.v12i1.4357},
url = {https://doi.org/10.11591/eei.v12i1.4357}
}RIS
TY - JOUR TI - Performance analysis of CMOS based analog circuit design with PVR variation AU - Pankaj P. Prajapati AU - Anilkumar J. Kshatriya AU - Sureshbhai L. Bharvad AU - Abhay B. Upadhyay PY - 2023 JO - Bulletin of Electrical Engineering and Informatics DO - 10.11591/eei.v12i1.4357 UR - https://doi.org/10.11591/eei.v12i1.4357 ER -
APA
Prajapati, P. P., Kshatriya, A. J., Bharvad, S. L., & Upadhyay, A. B. (2023). Performance analysis of CMOS based analog circuit design with PVR variation. Bulletin of Electrical Engineering and Informatics. https://doi.org/10.11591/eei.v12i1.4357
Source records
- crossref · retrieved 2026-09-25T06:01:31.755Z