Efficient reconfigurable parallel switching for low-density parity-check encoding and decoding

Divyashree Yamadur Venkatesh, Komala Mallikarjunaiah, Mallikarjunaswamy Srikantaswamy

Open source

DOI: 10.11591/ijai.v14.i1.pp260-269
Published: 2025-02-01
Container: IAES International Journal of Artificial Intelligence (IJ-AI)
Publisher: Institute of Advanced Engineering and Science
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.11591/ijai.v14.i1.pp260-269,
  title = {Efficient reconfigurable parallel switching for low-density  parity-check encoding and decoding},
  author = {Divyashree Yamadur Venkatesh and Komala Mallikarjunaiah and Mallikarjunaswamy Srikantaswamy},
  year = {2025},
  journal = {IAES International Journal of Artificial Intelligence (IJ-AI)},
  doi = {10.11591/ijai.v14.i1.pp260-269},
  url = {https://doi.org/10.11591/ijai.v14.i1.pp260-269}
}

RIS

TY  - JOUR
TI  - Efficient reconfigurable parallel switching for low-density  parity-check encoding and decoding
AU  - Divyashree Yamadur Venkatesh
AU  - Komala Mallikarjunaiah
AU  - Mallikarjunaswamy Srikantaswamy
PY  - 2025
JO  - IAES International Journal of Artificial Intelligence (IJ-AI)
DO  - 10.11591/ijai.v14.i1.pp260-269
UR  - https://doi.org/10.11591/ijai.v14.i1.pp260-269
ER  -

APA

Venkatesh, D. Y., Mallikarjunaiah, K., & Srikantaswamy, M. (2025). Efficient reconfigurable parallel switching for low-density parity-check encoding and decoding. IAES International Journal of Artificial Intelligence (IJ-AI). https://doi.org/10.11591/ijai.v14.i1.pp260-269

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crossref · retrieved 2026-09-26T00:19:21.276Z