High Speed Area Efficient FPGA Implementation of AES Algorithm

P. B. Mane, A. O. Mulani

Open source

DOI: 10.11591/ijres.v7.i3.pp157-165
Published: 2018-11-01
Container: International Journal of Reconfigurable and Embedded Systems (IJRES)
Publisher: Institute of Advanced Engineering and Science
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.11591/ijres.v7.i3.pp157-165,
  title = {High Speed Area Efficient FPGA Implementation of AES Algorithm},
  author = {P. B. Mane and A. O. Mulani},
  year = {2018},
  journal = {International Journal of Reconfigurable and Embedded Systems (IJRES)},
  doi = {10.11591/ijres.v7.i3.pp157-165},
  url = {https://doi.org/10.11591/ijres.v7.i3.pp157-165}
}

RIS

TY  - JOUR
TI  - High Speed Area Efficient FPGA Implementation of AES Algorithm
AU  - P. B. Mane
AU  - A. O. Mulani
PY  - 2018
JO  - International Journal of Reconfigurable and Embedded Systems (IJRES)
DO  - 10.11591/ijres.v7.i3.pp157-165
UR  - https://doi.org/10.11591/ijres.v7.i3.pp157-165
ER  -

APA

Mane, P. B., & Mulani, A. O. (2018). High Speed Area Efficient FPGA Implementation of AES Algorithm. International Journal of Reconfigurable and Embedded Systems (IJRES). https://doi.org/10.11591/ijres.v7.i3.pp157-165

Source records

crossref · retrieved 2026-09-27T10:12:59.163Z