Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances
- DOI
- 10.1166/jnn.2020.18768
- Published
- 2020-11-01
- Container
- Journal of Nanoscience and Nanotechnology
- Publisher
- American Scientific Publishers
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1166/jnn.2020.18768,
title = {Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances},
author = {Sang Ho Lee and Min Su Cho and Jun Hyeok Jung and Won Douk Jang and Hye Jin Mun and Jaewon Jang and Jin-Hyuk Bae and In Man Kang},
year = {2020},
journal = {Journal of Nanoscience and Nanotechnology},
doi = {10.1166/jnn.2020.18768},
url = {https://doi.org/10.1166/jnn.2020.18768}
}RIS
TY - JOUR TI - Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances AU - Sang Ho Lee AU - Min Su Cho AU - Jun Hyeok Jung AU - Won Douk Jang AU - Hye Jin Mun AU - Jaewon Jang AU - Jin-Hyuk Bae AU - In Man Kang PY - 2020 JO - Journal of Nanoscience and Nanotechnology DO - 10.1166/jnn.2020.18768 UR - https://doi.org/10.1166/jnn.2020.18768 ER -
APA
Lee, S. H., Cho, M. S., Jung, J. H., Jang, W. D., Mun, H. J., Jang, J., Bae, J., & Kang, I. M. (2020). Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances. Journal of Nanoscience and Nanotechnology. https://doi.org/10.1166/jnn.2020.18768
Source records
- crossref · retrieved 2026-09-25T01:08:03.311Z