A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

J Jency Rubia, GA Sathish Kumar

DOI: 10.1177/0020720918813836
Published: 2018-12-05
Container: International Journal of Electrical Engineering & Education
Publisher: SAGE Publications
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1177/0020720918813836,
  title = {A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm},
  author = {J Jency Rubia and GA Sathish Kumar},
  year = {2018},
  journal = {International Journal of Electrical Engineering \&amp; Education},
  doi = {10.1177/0020720918813836},
  url = {https://doi.org/10.1177/0020720918813836}
}

RIS

TY  - JOUR
TI  - A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm
AU  - J Jency Rubia
AU  - GA Sathish Kumar
PY  - 2018
JO  - International Journal of Electrical Engineering &amp; Education
DO  - 10.1177/0020720918813836
UR  - https://doi.org/10.1177/0020720918813836
ER  -

APA

Rubia, J. J., & Kumar, G. S. (2018). A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm. International Journal of Electrical Engineering & Education. https://doi.org/10.1177/0020720918813836

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crossref · retrieved 2026-09-25T10:42:27.361Z