Capacitive in-memory vector-matrix multiplication computing with charge-trap memcapacitors.

Yu J, Hwang H, Kim H, Choi WY

DOI: 10.1186/s40580-026-00575-9
Published: 2026 Sep 10
Container: Nano convergence
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.1186/s40580-026-00575-9,
  title = {Capacitive in-memory vector-matrix multiplication computing with charge-trap memcapacitors.},
  author = {Yu J and Hwang H and Kim H and Choi WY},
  year = {2026},
  journal = {Nano convergence},
  doi = {10.1186/s40580-026-00575-9},
  url = {https://doi.org/10.1186/s40580-026-00575-9}
}

RIS

TY  - JOUR
TI  - Capacitive in-memory vector-matrix multiplication computing with charge-trap memcapacitors.
AU  - Yu J
AU  - Hwang H
AU  - Kim H
AU  - Choi WY
PY  - 2026
JO  - Nano convergence
DO  - 10.1186/s40580-026-00575-9
UR  - https://doi.org/10.1186/s40580-026-00575-9
ER  -

APA

J, Y., H, H., H, K., & WY, C. (2026). Capacitive in-memory vector-matrix multiplication computing with charge-trap memcapacitors.. Nano convergence. https://doi.org/10.1186/s40580-026-00575-9

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pubmed · retrieved 2026-09-25T07:49:19.434Z