Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments

Moos, Thorben

Open source

DOI
10.13154/tches.v2019.i3.202-232
Published
May
Container
Transactions on Cryptographic Hardware and Embedded Systems
Publisher
IACR Transactions on Cryptographic Hardware and Embedded Systems
Open access
no

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BibTeX

@article{allodium:10.13154/tches.v2019.i3.202-232,
  title = {Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments},
  author = {Moos, Thorben},
  year = {2019},
  journal = {Transactions on Cryptographic Hardware and Embedded Systems},
  doi = {10.13154/tches.v2019.i3.202-232},
  url = {https://doi.org/10.13154/tches.v2019.i3.202-232}
}

RIS

TY  - JOUR
TI  - Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments
AU  - Moos, Thorben
PY  - 2019
JO  - Transactions on Cryptographic Hardware and Embedded Systems
DO  - 10.13154/tches.v2019.i3.202-232
UR  - https://doi.org/10.13154/tches.v2019.i3.202-232
ER  - 

APA

Thorben, M. (2019). Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments. Transactions on Cryptographic Hardware and Embedded Systems. https://doi.org/10.13154/tches.v2019.i3.202-232

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