Pipelined and conflict-free number theoretic transform accelerator for CRYSTALS-Kyber on FPGA

Ayesha Waris, Arshad Aziz, Bilal Muhammad Khan

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DOI: 10.1371/journal.pone.0333301
Published: 2025-11-11
Container: PLOS One
Publisher: Public Library of Science (PLoS)
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1371/journal.pone.0333301,
  title = {Pipelined and conflict-free number theoretic transform accelerator for CRYSTALS-Kyber on FPGA},
  author = {Ayesha Waris and Arshad Aziz and Bilal Muhammad Khan},
  year = {2025},
  journal = {PLOS One},
  doi = {10.1371/journal.pone.0333301},
  url = {https://doi.org/10.1371/journal.pone.0333301}
}

RIS

TY  - JOUR
TI  - Pipelined and conflict-free number theoretic transform accelerator for CRYSTALS-Kyber on FPGA
AU  - Ayesha Waris
AU  - Arshad Aziz
AU  - Bilal Muhammad Khan
PY  - 2025
JO  - PLOS One
DO  - 10.1371/journal.pone.0333301
UR  - https://doi.org/10.1371/journal.pone.0333301
ER  -

APA

Waris, A., Aziz, A., & Khan, B. M. (2025). Pipelined and conflict-free number theoretic transform accelerator for CRYSTALS-Kyber on FPGA. PLOS One. https://doi.org/10.1371/journal.pone.0333301

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crossref · retrieved 2026-11-10T09:03:14.699Z