Stacked Nanowire FET for CMOS Technology Scaling

Kodali D, Pant D, Udutha SC, Therese B, kanthale O.

DOI: 10.21203/rs.3.rs-5414655/v1
Published: 2024-11-26
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Cite this work

BibTeX

@article{allodium:10.21203/rs.3.rs-5414655/v1,
  title = {Stacked Nanowire FET for CMOS Technology Scaling},
  author = {Kodali D and  Pant D and  Udutha SC and  Therese B and  kanthale O.},
  year = {2024},
  doi = {10.21203/rs.3.rs-5414655/v1},
  url = {https://doi.org/10.21203/rs.3.rs-5414655/v1}
}

RIS

TY  - JOUR
TI  - Stacked Nanowire FET for CMOS Technology Scaling
AU  - Kodali D
AU  -  Pant D
AU  -  Udutha SC
AU  -  Therese B
AU  -  kanthale O.
PY  - 2024
DO  - 10.21203/rs.3.rs-5414655/v1
UR  - https://doi.org/10.21203/rs.3.rs-5414655/v1
ER  -

APA

D, K., D, P., SC, U., B, T., & O., K. (2024). Stacked Nanowire FET for CMOS Technology Scaling. https://doi.org/10.21203/rs.3.rs-5414655/v1

Source records

europe-pmc · retrieved 2026-09-26T07:57:09.614Z