Hybrid CMOS circuits with 2D transistors: Projected performance down to sub-1 nm technology nodes
- DOI
- 10.21203/rs.3.rs-6423846/v1
- Published
- 2025-05-06
- Container
- Not recorded
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.21203/rs.3.rs-6423846/v1,
title = {Hybrid CMOS circuits with 2D transistors: Projected performance down to sub-1 nm technology nodes},
author = {He Tian and Hengbin Ding and Peigen Zhang and Fumeng Yang and Anhan Liu and Yanming Liu and Zhujun Yao and Jiarui He},
year = {2025},
doi = {10.21203/rs.3.rs-6423846/v1},
url = {https://doi.org/10.21203/rs.3.rs-6423846/v1}
}RIS
TY - JOUR TI - Hybrid CMOS circuits with 2D transistors: Projected performance down to sub-1 nm technology nodes AU - He Tian AU - Hengbin Ding AU - Peigen Zhang AU - Fumeng Yang AU - Anhan Liu AU - Yanming Liu AU - Zhujun Yao AU - Jiarui He PY - 2025 DO - 10.21203/rs.3.rs-6423846/v1 UR - https://doi.org/10.21203/rs.3.rs-6423846/v1 ER -
APA
Tian, H., Ding, H., Zhang, P., Yang, F., Liu, A., Liu, Y., Yao, Z., & He, J. (2025). Hybrid CMOS circuits with 2D transistors: Projected performance down to sub-1 nm technology nodes. https://doi.org/10.21203/rs.3.rs-6423846/v1
Source records
- crossref · retrieved 2026-11-06T02:58:35.457Z