Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI
- DOI
- 10.21203/rs.3.rs-8486209/v1
- Published
- 2026-02-10
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- Not recorded
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.21203/rs.3.rs-8486209/v1,
title = {Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI},
author = {Young-Gi Song and Hae-Seong Jeong and Jae-Ha Kim and Sung-Yun Cho and Hyeok-Jung Kwon},
year = {2026},
doi = {10.21203/rs.3.rs-8486209/v1},
url = {https://doi.org/10.21203/rs.3.rs-8486209/v1}
}RIS
TY - JOUR TI - Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI AU - Young-Gi Song AU - Hae-Seong Jeong AU - Jae-Ha Kim AU - Sung-Yun Cho AU - Hyeok-Jung Kwon PY - 2026 DO - 10.21203/rs.3.rs-8486209/v1 UR - https://doi.org/10.21203/rs.3.rs-8486209/v1 ER -
APA
Song, Y., Jeong, H., Kim, J., Cho, S., & Kwon, H. (2026). Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI. https://doi.org/10.21203/rs.3.rs-8486209/v1
Source records
- crossref · retrieved 2026-09-25T21:45:34.927Z