E-BIST: Enhanced test-per-clock BIST architecture

Y. Son, J. Chong, G. Russell

DOI: 10.25405/ncl.34605027.v1
Published: 2026
Container: Not recorded
Publisher: Newcastle University
Open access: no

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Cite this work

BibTeX

@article{allodium:10.25405/ncl.34605027.v1,
  title = {E-BIST: Enhanced test-per-clock BIST architecture},
  author = {Y. Son and J. Chong and G. Russell},
  year = {2026},
  doi = {10.25405/ncl.34605027.v1},
  url = {https://doi.org/10.25405/ncl.34605027.v1}
}

RIS

TY  - JOUR
TI  - E-BIST: Enhanced test-per-clock BIST architecture
AU  - Y. Son
AU  - J. Chong
AU  - G. Russell
PY  - 2026
DO  - 10.25405/ncl.34605027.v1
UR  - https://doi.org/10.25405/ncl.34605027.v1
ER  -

APA

Son, Y., Chong, J., & Russell, G. (2026). E-BIST: Enhanced test-per-clock BIST architecture. https://doi.org/10.25405/ncl.34605027.v1

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datacite · retrieved 2026-11-08T22:36:55.155Z