Modular Verification for Network-On-Chip Designs Using Probabilistic Verification and Assume-Guarantee Reasoning

Waddoups, Nicholas

DOI: 10.26076/c04e-54f4
Published: 2026
Container: Not recorded
Publisher: Utah State University
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.26076/c04e-54f4,
  title = {Modular Verification for Network-On-Chip Designs Using Probabilistic Verification and Assume-Guarantee Reasoning},
  author = {Waddoups, Nicholas},
  year = {2026},
  doi = {10.26076/c04e-54f4},
  url = {https://doi.org/10.26076/c04e-54f4}
}

RIS

TY  - JOUR
TI  - Modular Verification for Network-On-Chip Designs Using Probabilistic Verification and Assume-Guarantee Reasoning
AU  - Waddoups, Nicholas
PY  - 2026
DO  - 10.26076/c04e-54f4
UR  - https://doi.org/10.26076/c04e-54f4
ER  -

APA

Nicholas, W. (2026). Modular Verification for Network-On-Chip Designs Using Probabilistic Verification and Assume-Guarantee Reasoning. https://doi.org/10.26076/c04e-54f4

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datacite · retrieved 2026-11-10T06:42:39.039Z