Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Beomjun Kim, Gyeongseob Seo, Myungsuk Kim

Open source

DOI: 10.3390/eng5010027
Published: 03
Container: Eng
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.3390/eng5010027,
  title = {Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory},
  author = {Beomjun Kim and Gyeongseob Seo and Myungsuk Kim},
  year = {2024},
  journal = {Eng},
  doi = {10.3390/eng5010027},
  url = {https://doi.org/10.3390/eng5010027}
}

RIS

TY  - JOUR
TI  - Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory
AU  - Beomjun Kim
AU  - Gyeongseob Seo
AU  - Myungsuk Kim
PY  - 2024
JO  - Eng
DO  - 10.3390/eng5010027
UR  - https://doi.org/10.3390/eng5010027
ER  -

APA

Kim, B., Seo, G., & Kim, M. (2024). Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory. Eng. https://doi.org/10.3390/eng5010027

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doaj · retrieved 2026-09-24T22:14:33.658Z