Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit
- DOI
- 10.3390/engproc2025089031
- Published
- 2025-02-28
- Container
- 2024 IEEE 7th International Conference on Knowledge Innovation and Invention
- Publisher
- MDPI
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.3390/engproc2025089031,
title = {Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit},
author = {Mao-Hsu Yen and Yih-Hsia Lin and Tzu-Feng Lin and Yu-Hui Chen and Yuan-Fu Ku and Chien-Ting Kao},
year = {2025},
journal = {2024 IEEE 7th International Conference on Knowledge Innovation and Invention},
doi = {10.3390/engproc2025089031},
url = {https://doi.org/10.3390/engproc2025089031}
}RIS
TY - JOUR TI - Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit AU - Mao-Hsu Yen AU - Yih-Hsia Lin AU - Tzu-Feng Lin AU - Yu-Hui Chen AU - Yuan-Fu Ku AU - Chien-Ting Kao PY - 2025 JO - 2024 IEEE 7th International Conference on Knowledge Innovation and Invention DO - 10.3390/engproc2025089031 UR - https://doi.org/10.3390/engproc2025089031 ER -
APA
Yen, M., Lin, Y., Lin, T., Chen, Y., Ku, Y., & Kao, C. (2025). Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit. 2024 IEEE 7th International Conference on Knowledge Innovation and Invention. https://doi.org/10.3390/engproc2025089031
Source records
- crossref · retrieved 2026-09-27T03:56:30.173Z