A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits
- DOI
- 10.3390/jlpea14010005
- Published
- 2024-01-14
- Container
- Journal of Low Power Electronics and Applications
- Publisher
- MDPI AG
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.3390/jlpea14010005,
title = {A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits},
author = {Dipayan Mazumder and Mithun Datta and Alexander C. Bodoh and Ashiq A. Sakib},
year = {2024},
journal = {Journal of Low Power Electronics and Applications},
doi = {10.3390/jlpea14010005},
url = {https://doi.org/10.3390/jlpea14010005}
}RIS
TY - JOUR TI - A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits AU - Dipayan Mazumder AU - Mithun Datta AU - Alexander C. Bodoh AU - Ashiq A. Sakib PY - 2024 JO - Journal of Low Power Electronics and Applications DO - 10.3390/jlpea14010005 UR - https://doi.org/10.3390/jlpea14010005 ER -
APA
Mazumder, D., Datta, M., Bodoh, A. C., & Sakib, A. A. (2024). A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits. Journal of Low Power Electronics and Applications. https://doi.org/10.3390/jlpea14010005
Source records
- crossref · retrieved 2026-09-25T20:58:06.930Z