Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests.

Lee CC

DOI: 10.3390/ma10101220
Published: 2017 Oct 24
Container: Materials (Basel, Switzerland)
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.3390/ma10101220,
  title = {Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests.},
  author = {Lee CC},
  year = {2017},
  journal = {Materials (Basel, Switzerland)},
  doi = {10.3390/ma10101220},
  url = {https://doi.org/10.3390/ma10101220}
}

RIS

TY  - JOUR
TI  - Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests.
AU  - Lee CC
PY  - 2017
JO  - Materials (Basel, Switzerland)
DO  - 10.3390/ma10101220
UR  - https://doi.org/10.3390/ma10101220
ER  -

APA

CC, L. (2017). Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests.. Materials (Basel, Switzerland). https://doi.org/10.3390/ma10101220

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pubmed · retrieved 2026-11-10T07:03:58.897Z