SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction.

Li T, Tian J, Qi J

DOI: 10.3390/mi17030342
Published: 2026 Mar 11
Container: Micromachines
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.3390/mi17030342,
  title = {SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction.},
  author = {Li T and Tian J and Qi J},
  year = {2026},
  journal = {Micromachines},
  doi = {10.3390/mi17030342},
  url = {https://doi.org/10.3390/mi17030342}
}

RIS

TY  - JOUR
TI  - SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction.
AU  - Li T
AU  - Tian J
AU  - Qi J
PY  - 2026
JO  - Micromachines
DO  - 10.3390/mi17030342
UR  - https://doi.org/10.3390/mi17030342
ER  -

APA

T, L., J, T., & J, Q. (2026). SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction.. Micromachines. https://doi.org/10.3390/mi17030342

Source records

pubmed · retrieved 2026-09-26T02:50:34.451Z