A 2-GS/s 35.9-fJ/conv.-step Voltage-Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS.

Chang Y, Zhang C, Yang Y, Zhang C, Liu M, Chen D, Yang Y

Open source

DOI
10.3390/mi17040495
Published
2026 Apr 17
Container
Micromachines
Publisher
Not recorded
Open access
yes

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BibTeX

@article{allodium:10.3390/mi17040495,
  title = {A 2-GS/s 35.9-fJ/conv.-step Voltage-Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS.},
  author = {Chang Y and Zhang C and Yang Y and Zhang C and Liu M and Chen D and Yang Y},
  year = {2026},
  journal = {Micromachines},
  doi = {10.3390/mi17040495},
  url = {https://doi.org/10.3390/mi17040495}
}

RIS

TY  - JOUR
TI  - A 2-GS/s 35.9-fJ/conv.-step Voltage-Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS.
AU  - Chang Y
AU  - Zhang C
AU  - Yang Y
AU  - Zhang C
AU  - Liu M
AU  - Chen D
AU  - Yang Y
PY  - 2026
JO  - Micromachines
DO  - 10.3390/mi17040495
UR  - https://doi.org/10.3390/mi17040495
ER  - 

APA

Y, C., C, Z., Y, Y., C, Z., M, L., D, C., & Y, Y. (2026). A 2-GS/s 35.9-fJ/conv.-step Voltage-Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS.. Micromachines. https://doi.org/10.3390/mi17040495

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