A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS
- DOI
- 10.3390/mi17040495
- Published
- 2026-04-17
- Container
- Micromachines
- Publisher
- MDPI AG
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.3390/mi17040495,
title = {A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS},
author = {Yuan Chang and Chenghao Zhang and Yihang Yang and Chaoyang Zhang and Maliang Liu and Dongdong Chen and Yintang Yang},
year = {2026},
journal = {Micromachines},
doi = {10.3390/mi17040495},
url = {https://doi.org/10.3390/mi17040495}
}RIS
TY - JOUR TI - A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS AU - Yuan Chang AU - Chenghao Zhang AU - Yihang Yang AU - Chaoyang Zhang AU - Maliang Liu AU - Dongdong Chen AU - Yintang Yang PY - 2026 JO - Micromachines DO - 10.3390/mi17040495 UR - https://doi.org/10.3390/mi17040495 ER -
APA
Chang, Y., Zhang, C., Yang, Y., Zhang, C., Liu, M., Chen, D., & Yang, Y. (2026). A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS. Micromachines. https://doi.org/10.3390/mi17040495
Source records
- crossref · retrieved 2026-11-10T07:09:12.453Z