SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators.

Wang H, Yang S, Chen Z, Sun H, Shen Y, Li H, Jiang Z, Li Y, Liang X

DOI: 10.3390/mi17050535
Published: 2026 Apr 27
Container: Micromachines
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.3390/mi17050535,
  title = {SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators.},
  author = {Wang H and Yang S and Chen Z and Sun H and Shen Y and Li H and Jiang Z and Li Y and Liang X},
  year = {2026},
  journal = {Micromachines},
  doi = {10.3390/mi17050535},
  url = {https://doi.org/10.3390/mi17050535}
}

RIS

TY  - JOUR
TI  - SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators.
AU  - Wang H
AU  - Yang S
AU  - Chen Z
AU  - Sun H
AU  - Shen Y
AU  - Li H
AU  - Jiang Z
AU  - Li Y
AU  - Liang X
PY  - 2026
JO  - Micromachines
DO  - 10.3390/mi17050535
UR  - https://doi.org/10.3390/mi17050535
ER  -

APA

H, W., S, Y., Z, C., H, S., Y, S., H, L., Z, J., Y, L., & X, L. (2026). SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators.. Micromachines. https://doi.org/10.3390/mi17050535

Source records

pubmed · retrieved 2026-09-25T17:12:15.584Z