A Wafer-Level Stacking Scheme Based on Hybrid Etching and Low-Temperature Bonding for High-Performance MEMS Devices.

Li P, Yan X, Yang Y, Meng L, Zhang X, Wang H, Lu Q

Open source

DOI
10.3390/mi17060651
Published
2026 May 25
Container
Micromachines
Publisher
Not recorded
Open access
yes

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BibTeX

@article{allodium:10.3390/mi17060651,
  title = {A Wafer-Level Stacking Scheme Based on Hybrid Etching and Low-Temperature Bonding for High-Performance MEMS Devices.},
  author = {Li P and Yan X and Yang Y and Meng L and Zhang X and Wang H and Lu Q},
  year = {2026},
  journal = {Micromachines},
  doi = {10.3390/mi17060651},
  url = {https://doi.org/10.3390/mi17060651}
}

RIS

TY  - JOUR
TI  - A Wafer-Level Stacking Scheme Based on Hybrid Etching and Low-Temperature Bonding for High-Performance MEMS Devices.
AU  - Li P
AU  - Yan X
AU  - Yang Y
AU  - Meng L
AU  - Zhang X
AU  - Wang H
AU  - Lu Q
PY  - 2026
JO  - Micromachines
DO  - 10.3390/mi17060651
UR  - https://doi.org/10.3390/mi17060651
ER  - 

APA

P, L., X, Y., Y, Y., L, M., X, Z., H, W., & Q, L. (2026). A Wafer-Level Stacking Scheme Based on Hybrid Etching and Low-Temperature Bonding for High-Performance MEMS Devices.. Micromachines. https://doi.org/10.3390/mi17060651

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