Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs.

Ma H, Gu S, Zhai M, Liu H

DOI: 10.3390/nano16110653
Published: 2026 May 22
Container: Nanomaterials (Basel, Switzerland)
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.3390/nano16110653,
  title = {Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs.},
  author = {Ma H and Gu S and Zhai M and Liu H},
  year = {2026},
  journal = {Nanomaterials (Basel, Switzerland)},
  doi = {10.3390/nano16110653},
  url = {https://doi.org/10.3390/nano16110653}
}

RIS

TY  - JOUR
TI  - Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs.
AU  - Ma H
AU  - Gu S
AU  - Zhai M
AU  - Liu H
PY  - 2026
JO  - Nanomaterials (Basel, Switzerland)
DO  - 10.3390/nano16110653
UR  - https://doi.org/10.3390/nano16110653
ER  -

APA

H, M., S, G., M, Z., & H, L. (2026). Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs.. Nanomaterials (Basel, Switzerland). https://doi.org/10.3390/nano16110653

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pubmed · retrieved 2026-09-25T02:40:44.067Z