A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.

Algredo-Badillo I, Morales-Sandoval M, Medina-Santiago A, Hernández-Gracidas CA, Lobato-Baez M, Morales-Rosales LA

DOI: 10.3390/s22135028
Published: 2022 Jul 3
Container: Sensors (Basel, Switzerland)
Publisher: Not recorded
Open access: yes

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BibTeX

@article{allodium:10.3390/s22135028,
  title = {A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.},
  author = {Algredo-Badillo I and Morales-Sandoval M and Medina-Santiago A and Hernández-Gracidas CA and Lobato-Baez M and Morales-Rosales LA},
  year = {2022},
  journal = {Sensors (Basel, Switzerland)},
  doi = {10.3390/s22135028},
  url = {https://doi.org/10.3390/s22135028}
}

RIS

TY  - JOUR
TI  - A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.
AU  - Algredo-Badillo I
AU  - Morales-Sandoval M
AU  - Medina-Santiago A
AU  - Hernández-Gracidas CA
AU  - Lobato-Baez M
AU  - Morales-Rosales LA
PY  - 2022
JO  - Sensors (Basel, Switzerland)
DO  - 10.3390/s22135028
UR  - https://doi.org/10.3390/s22135028
ER  -

APA

I, A., M, M., A, M., CA, H., M, L., & LA, M. (2022). A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.. Sensors (Basel, Switzerland). https://doi.org/10.3390/s22135028

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pubmed · retrieved 2026-09-24T20:02:29.845Z