Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods

Unknown, Dr. C. Arunabala, A. Lohithakshi, Unknown, D. Jyothsna, Unknown, CH. Pranathi, Unknown, A. Navaneetha, Unknown

Open source

DOI: 10.35940/ijitee.e9850.0411522
Published: 2022-04-30
Container: International Journal of Innovative Technology and Exploring Engineering
Publisher: Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.35940/ijitee.e9850.0411522,
  title = {Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods},
  author = {Unknown and Dr. C. Arunabala and A. Lohithakshi and Unknown and D. Jyothsna and Unknown and CH. Pranathi and Unknown and A. Navaneetha and Unknown},
  year = {2022},
  journal = {International Journal of Innovative Technology and Exploring Engineering},
  doi = {10.35940/ijitee.e9850.0411522},
  url = {https://doi.org/10.35940/ijitee.e9850.0411522}
}

RIS

TY  - JOUR
TI  - Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
AU  - Unknown
AU  - Dr. C. Arunabala
AU  - A. Lohithakshi
AU  - Unknown
AU  - D. Jyothsna
AU  - Unknown
AU  - CH. Pranathi
AU  - Unknown
AU  - A. Navaneetha
AU  - Unknown
PY  - 2022
JO  - International Journal of Innovative Technology and Exploring Engineering
DO  - 10.35940/ijitee.e9850.0411522
UR  - https://doi.org/10.35940/ijitee.e9850.0411522
ER  -

APA

Unknown, Arunabala, D. C., Lohithakshi, A., Unknown, Jyothsna, D., Unknown, Pranathi, C., Unknown, Navaneetha, A., & Unknown (2022). Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods. International Journal of Innovative Technology and Exploring Engineering. https://doi.org/10.35940/ijitee.e9850.0411522

Source records

crossref · retrieved 2026-11-06T19:49:12.096Z