Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

C.-S. HOO, K. JEEVAN, V. GANAPATHY, H. RAMIAH

Open source

DOI: 10.4316/aece.2013.01002
Published: 2013
Container: Advances in Electrical and Computer Engineering
Publisher: Universitatea Stefan cel Mare din Suceava
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.4316/aece.2013.01002,
  title = {Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer},
  author = {C.-S. HOO and K. JEEVAN and V. GANAPATHY and H. RAMIAH},
  year = {2013},
  journal = {Advances in Electrical and Computer Engineering},
  doi = {10.4316/aece.2013.01002},
  url = {https://doi.org/10.4316/aece.2013.01002}
}

RIS

TY  - JOUR
TI  - Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer
AU  - C.-S. HOO
AU  - K. JEEVAN
AU  - V. GANAPATHY
AU  - H. RAMIAH
PY  - 2013
JO  - Advances in Electrical and Computer Engineering
DO  - 10.4316/aece.2013.01002
UR  - https://doi.org/10.4316/aece.2013.01002
ER  -

APA

HOO, C., JEEVAN, K., GANAPATHY, V., & RAMIAH, H. (2013). Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer. Advances in Electrical and Computer Engineering. https://doi.org/10.4316/aece.2013.01002

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crossref · retrieved 2026-09-25T01:40:54.244Z