A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
- DOI
- 10.48550/arxiv.2404.15823
- Published
- 2024
- Container
- Not recorded
- Publisher
- arXiv
- Open access
- yes
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Cite this work
BibTeX
@article{allodium:10.48550/arxiv.2404.15823,
title = {A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator},
author = {Bause, Oliver and Bernardo, Paul Palomero and Bringmann, Oliver},
year = {2024},
doi = {10.48550/arxiv.2404.15823},
url = {https://doi.org/10.48550/arxiv.2404.15823}
}RIS
TY - JOUR TI - A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator AU - Bause, Oliver AU - Bernardo, Paul Palomero AU - Bringmann, Oliver PY - 2024 DO - 10.48550/arxiv.2404.15823 UR - https://doi.org/10.48550/arxiv.2404.15823 ER -
APA
Oliver, B., Palomero, B. P., & Oliver, B. (2024). A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator. https://doi.org/10.48550/arxiv.2404.15823
Source records
- datacite · retrieved 2026-09-25T14:26:45.765Z