An FPGA-ASIC Co-Design Framework for Capacity-Constrained Physics-Based Ising Chips
- DOI
- 10.48550/arxiv.2602.15985
- Published
- 2026
- Container
- Not recorded
- Publisher
- arXiv
- Open access
- no
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Cite this work
BibTeX
@article{allodium:10.48550/arxiv.2602.15985,
title = {An FPGA-ASIC Co-Design Framework for Capacity-Constrained Physics-Based Ising Chips},
author = {Yin, Ruihong and Zheng, Yue and Li, Chaohui and Efe, Ahmet and Kumar, Abhimanyu and Zeng, Ziqing and Karpuzcu, Ulya R. and Sapatnekar, Sachin S. and Kim, Chris H.},
year = {2026},
doi = {10.48550/arxiv.2602.15985},
url = {https://doi.org/10.48550/arxiv.2602.15985}
}RIS
TY - JOUR TI - An FPGA-ASIC Co-Design Framework for Capacity-Constrained Physics-Based Ising Chips AU - Yin, Ruihong AU - Zheng, Yue AU - Li, Chaohui AU - Efe, Ahmet AU - Kumar, Abhimanyu AU - Zeng, Ziqing AU - Karpuzcu, Ulya R. AU - Sapatnekar, Sachin S. AU - Kim, Chris H. PY - 2026 DO - 10.48550/arxiv.2602.15985 UR - https://doi.org/10.48550/arxiv.2602.15985 ER -
APA
Ruihong, Y., Yue, Z., Chaohui, L., Ahmet, E., Abhimanyu, K., Ziqing, Z., R., K. U., S., S. S., & H., K. C. (2026). An FPGA-ASIC Co-Design Framework for Capacity-Constrained Physics-Based Ising Chips. https://doi.org/10.48550/arxiv.2602.15985
Source records
- datacite · retrieved 2026-09-25T20:45:08.177Z