STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design

Wang, Kainan, Yang, Chengyi, Liu, Lei, Yu, Chengting, Ang, Yee Sin, Wang, Bo, Wang, Aili

Open source

DOI
10.48550/arxiv.2610.19973
Published
2026
Container
Not recorded
Publisher
arXiv
Open access
no

Credibility signals

limited evidence Score 41/100 under policy 1.0.0. This is a metadata assessment, not a judgment of the paper's conclusions.

Show all credibility signals

Cite this work

BibTeX

@article{allodium:10.48550/arxiv.2610.19973,
  title = {STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design},
  author = {Wang, Kainan and Yang, Chengyi and Liu, Lei and Yu, Chengting and Ang, Yee Sin and Wang, Bo and Wang, Aili},
  year = {2026},
  doi = {10.48550/arxiv.2610.19973},
  url = {https://doi.org/10.48550/arxiv.2610.19973}
}

RIS

TY  - JOUR
TI  - STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design
AU  - Wang, Kainan
AU  - Yang, Chengyi
AU  - Liu, Lei
AU  - Yu, Chengting
AU  - Ang, Yee Sin
AU  - Wang, Bo
AU  - Wang, Aili
PY  - 2026
DO  - 10.48550/arxiv.2610.19973
UR  - https://doi.org/10.48550/arxiv.2610.19973
ER  -

APA

Kainan, W., Chengyi, Y., Lei, L., Chengting, Y., Sin, A. Y., Bo, W., & Aili, W. (2026). STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design. https://doi.org/10.48550/arxiv.2610.19973

Source records