An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance
- DOI
- 10.5121/vlsic.2012.3101
- Published
- 2012-02-29
- Container
- International Journal of VLSI Design & Communication Systems
- Publisher
- Academy and Industry Research Collaboration Center (AIRCC)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.5121/vlsic.2012.3101,
title = {An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance},
author = {Brinda Bhowmick},
year = {2012},
journal = {International Journal of VLSI Design \& Communication Systems},
doi = {10.5121/vlsic.2012.3101},
url = {https://doi.org/10.5121/vlsic.2012.3101}
}RIS
TY - JOUR TI - An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance AU - Brinda Bhowmick PY - 2012 JO - International Journal of VLSI Design & Communication Systems DO - 10.5121/vlsic.2012.3101 UR - https://doi.org/10.5121/vlsic.2012.3101 ER -
APA
Bhowmick, B. (2012). An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance. International Journal of VLSI Design & Communication Systems. https://doi.org/10.5121/vlsic.2012.3101
Source records
- crossref · retrieved 2026-11-10T06:50:06.642Z