Dual-Link Hierarchical Cluster-Based Interconnect Architecture For 3D Network On Chip
- DOI
- 10.5281/zenodo.1063135
- Published
- 2010
- Container
- Not recorded
- Publisher
- Zenodo
- Open access
- yes
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Cite this work
BibTeX
@article{allodium:10.5281/zenodo.1063135,
title = {Dual-Link Hierarchical Cluster-Based Interconnect Architecture For 3D Network On Chip},
author = {Sun, Guang and Li, Yong and Yuanyuan Zhang and Shijun Lin and Su, Li and Depeng Jin and Lieguang Zeng},
year = {2010},
doi = {10.5281/zenodo.1063135},
url = {https://doi.org/10.5281/zenodo.1063135}
}RIS
TY - JOUR TI - Dual-Link Hierarchical Cluster-Based Interconnect Architecture For 3D Network On Chip AU - Sun, Guang AU - Li, Yong AU - Yuanyuan Zhang AU - Shijun Lin AU - Su, Li AU - Depeng Jin AU - Lieguang Zeng PY - 2010 DO - 10.5281/zenodo.1063135 UR - https://doi.org/10.5281/zenodo.1063135 ER -
APA
Guang, S., Yong, L., Zhang, Y., Lin, S., Li, S., Jin, D., & Zeng, L. (2010). Dual-Link Hierarchical Cluster-Based Interconnect Architecture For 3D Network On Chip. https://doi.org/10.5281/zenodo.1063135