Building and analyzing processing graphs on FPGAs with strong time and hardware constraints

Ke Du

Open source

DOI: 10.70675/2db7bda9z874cz4787z8396z5de6b1106998
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Publisher: Agence Bibliographique de l'Enseignement Supérieur
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Cite this work

BibTeX

@article{allodium:10.70675/2db7bda9z874cz4787z8396z5de6b1106998,
  title = {Building and analyzing processing graphs on FPGAs with strong time and hardware constraints},
  author = {Ke Du},
  doi = {10.70675/2db7bda9z874cz4787z8396z5de6b1106998},
  url = {https://doi.org/10.70675/2db7bda9z874cz4787z8396z5de6b1106998}
}

RIS

TY  - JOUR
TI  - Building and analyzing processing graphs on FPGAs with strong time and hardware constraints
AU  - Ke Du
DO  - 10.70675/2db7bda9z874cz4787z8396z5de6b1106998
UR  - https://doi.org/10.70675/2db7bda9z874cz4787z8396z5de6b1106998
ER  -

APA

Du, K. (n.d.). Building and analyzing processing graphs on FPGAs with strong time and hardware constraints. https://doi.org/10.70675/2db7bda9z874cz4787z8396z5de6b1106998

Source records

crossref · retrieved 2026-09-26T19:25:35.573Z