Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques

Dmitry Burlyaev

Open source

DOI: 10.70675/440c62dcz4d54z4f8ez9241za00c078a5280
Published: Not recorded
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Publisher: Agence Bibliographique de l'Enseignement Supérieur
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Cite this work

BibTeX

@article{allodium:10.70675/440c62dcz4d54z4f8ez9241za00c078a5280,
  title = {Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques},
  author = {Dmitry Burlyaev},
  doi = {10.70675/440c62dcz4d54z4f8ez9241za00c078a5280},
  url = {https://doi.org/10.70675/440c62dcz4d54z4f8ez9241za00c078a5280}
}

RIS

TY  - JOUR
TI  - Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques
AU  - Dmitry Burlyaev
DO  - 10.70675/440c62dcz4d54z4f8ez9241za00c078a5280
UR  - https://doi.org/10.70675/440c62dcz4d54z4f8ez9241za00c078a5280
ER  -

APA

Burlyaev, D. (n.d.). Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques. https://doi.org/10.70675/440c62dcz4d54z4f8ez9241za00c078a5280

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crossref · retrieved 2026-11-10T19:59:47.817Z