An electronic system level modeling approach for the design and verification of low-power systems-on chip

Ons Mbarek

Open source

DOI: 10.70675/947985f7z7cd3z4b19z8928z3e615613d680
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Publisher: Agence Bibliographique de l'Enseignement Supérieur
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Cite this work

BibTeX

@article{allodium:10.70675/947985f7z7cd3z4b19z8928z3e615613d680,
  title = {An electronic system level modeling approach for the design and verification of low-power systems-on chip},
  author = {Ons Mbarek},
  doi = {10.70675/947985f7z7cd3z4b19z8928z3e615613d680},
  url = {https://doi.org/10.70675/947985f7z7cd3z4b19z8928z3e615613d680}
}

RIS

TY  - JOUR
TI  - An electronic system level modeling approach for the design and verification of low-power systems-on chip
AU  - Ons Mbarek
DO  - 10.70675/947985f7z7cd3z4b19z8928z3e615613d680
UR  - https://doi.org/10.70675/947985f7z7cd3z4b19z8928z3e615613d680
ER  -

APA

Mbarek, O. (n.d.). An electronic system level modeling approach for the design and verification of low-power systems-on chip. https://doi.org/10.70675/947985f7z7cd3z4b19z8928z3e615613d680

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crossref · retrieved 2026-11-07T23:26:54.407Z