PLL Phase Noise & Jitter Modeling, for High Speed Serial Links

Klodjan Bidaj

DOI: 10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0
Published: 2016-11-30
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Open access: yes

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Cite this work

BibTeX

@article{allodium:10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0,
  title = {PLL Phase Noise \& Jitter Modeling, for High Speed Serial Links},
  author = {Klodjan Bidaj},
  year = {2016},
  doi = {10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0},
  url = {https://doi.org/10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0}
}

RIS

TY  - JOUR
TI  - PLL Phase Noise & Jitter Modeling, for High Speed Serial Links
AU  - Klodjan Bidaj
PY  - 2016
DO  - 10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0
UR  - https://doi.org/10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0
ER  -

APA

Bidaj, K. (2016). PLL Phase Noise & Jitter Modeling, for High Speed Serial Links. https://doi.org/10.70675/a2c86d9bzc73bz404dza448z4410475c5fe0

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hal · retrieved 2026-11-10T18:16:02.339Z