A VLSI ARCHITECTURE AND THE FPGA IMPLEMENTATION FOR MULTI-RATE LDPC DECODING
- DOI
- 10.71548/8174
- Published
- 2009
- Container
- Not recorded
- Publisher
- McMaster University
- Open access
- no
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limited evidence Score 43/100 under policy 1.0.0. This is a metadata assessment, not a judgment of the paper's conclusions.
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Cite this work
BibTeX
@article{allodium:10.71548/8174,
title = {A VLSI ARCHITECTURE AND THE FPGA IMPLEMENTATION FOR MULTI-RATE LDPC DECODING},
author = {Jobes, Mark},
year = {2009},
doi = {10.71548/8174},
url = {https://doi.org/10.71548/8174}
}RIS
TY - JOUR TI - A VLSI ARCHITECTURE AND THE FPGA IMPLEMENTATION FOR MULTI-RATE LDPC DECODING AU - Jobes, Mark PY - 2009 DO - 10.71548/8174 UR - https://doi.org/10.71548/8174 ER -
APA
Mark, J. (2009). A VLSI ARCHITECTURE AND THE FPGA IMPLEMENTATION FOR MULTI-RATE LDPC DECODING. https://doi.org/10.71548/8174
Source records
- datacite · retrieved 2026-09-24T23:43:40.824Z