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A sub-1ps/sub rms/ jitter 1-5GHz 0.13 µm CMOS PLL using a passive feedforward loop filter with noiseless resistor multiplication [frequency synthesizer application]
- Type
- Retraction
- Notice date
- 8/8/2005 0:00
- Journal
- 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium
- Publisher
- IEEE: Institute of Electrical and Electronics Engineers
- Notice DOI
- 10.1109/rfic.2005.1489633
- Original paper DOI
- 10.1109/rfic.2005.1489633
Reasons