A -86dBc reference spurs 1-5GHz 0.13µm CMOS PLL using a dual-path sampled loop filter architecture
- Type
- Retraction
- Notice date
- 7/25/2005 0:00
- Journal
- 2005 Symposium on VLSI Circuits
- Publisher
- IEEE: Institute of Electrical and Electronics Engineers
- Notice DOI
- 10.1109/vlsic.2005.1469378
- Original paper DOI
- 10.1109/vlsic.2005.1469378