A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation
- Type
- Retraction
- Notice date
- 1/3/2005 0:00
- Journal
- IEEE Journal of Solid-State Circuits
- Publisher
- IEEE: Institute of Electrical and Electronics Engineers
- Notice DOI
- 10.1109/jssc.2004.838004
- Original paper DOI
- 10.1109/jssc.2004.838004
Reasons
- False/Forged Authorship
- Falsification/Fabrication of Data
- Investigation by Journal/Publisher
- Misconduct by Author