A 160-2550MHz CMOS active clock deskewing PLL using analog phase interpolation
- Type
- Retraction
- Notice date
- 9/13/2004 0:00
- Journal
- 2004 IEEE International Solid-State Circuits Conference
- Publisher
- IEEE: Institute of Electrical and Electronics Engineers
- Notice DOI
- 10.1109/isscc.2004.1332736
- Original paper DOI
- 10.1109/isscc.2004.1332736