A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC
- Type
- Retraction
- Notice date
- 1/25/2014 0:00
- Journal
- IEICE Electronics Express
- Publisher
- The Institute of Electronics, Information and Communication Engineers
- Notice DOI
- 10.1587/elex.11.20148002
- Original paper DOI
- 10.1587/elex.9.1237