Electrostatic Discharge in Electronics
This cluster of papers focuses on the design, analysis, and modeling of electrostatic discharge (ESD) protection in integrated circuits, particularly in CMOS technology. It covers topics such as SCR devices, LDMOS design, RF ESD protection, TLP calibration, high-voltage ESD solutions, and latchup immunity. The papers also discuss on-chip protection strategies and system-level ESD testing.
Papers listed on taxonomy pages are the top few works per node from the OpenAlex snapshot. That list is not exhaustive and is not an endorsement. The topic map and the journal registry remain separate: there is still no authoritative topic-to-venue or topic-to-organization edge. Search is a lexical lookup, not a claim that a venue publishes a topic.